(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of providing improved damascene metal line adhesion to the line trench by modifying the trench profile.
(2) Description of the Prior Art
In fabricating very and ultra large scale integration (VLSI and ULSI) circuits, one of the more important aspects of this fabrication is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The continued requirements for device performance improvement that is achieved by continued reductions in device feature size require responsive changes in interconnect technology. The spacing between interconnect lines that are used in high density devices is at this time reduced to 0.35 microns or less. This brings with it increased demands on the profiles and the reliability of the metal interconnect lines.
Conventional methods of forming interconnect lines start with the deposition of a layer of insulation over a semiconductor surface, typically the surface of a single crystal silicon substrate. Openings for via or contact connections are created in this layer of insulation. A layer of metal is deposited over the surface of the layer of insulation, forming a planar surface and filling the via and contact openings. A layer of photoresist is next deposited over the metal layer, the photoresist is patterned for the interconnect line trenches. The layer of metal is etched in accordance with the pattern that has been created in the photoresist thus forming the interconnect line network. The spaces that have been created in the layer of metal (by the etch of the metal layer) are filled with a layer of (intra-metal) dielectric that may or may not be planarized.
The invention specifically addresses the fabrication of conductive lines and vias using the damascene process. Using the dual damascene process, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with a multiplicity of openings for the conductive lines and vias. The openings are simultaneously filled with a metal, such as aluminum, and serve to interconnect the active and/or the passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed.
In the standard dual damascene process an insulating layer is deposited over the surface of a substrate and coated with a layer of photoresist, the photoresist is exposed through a via mask, which contains an image pattern of the via openings. The via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist is then exposed through an interconnect line pattern mask with an image pattern of conductive line openings. The second exposure of the interconnecting line pattern is aligned with the via mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. The metal is now polished back to form an inlaid planar dual damascene structure.
Critical to a good dual damascene structure is that the edges of the via openings in the lower half of the insulating layer are clearly defined. Furthermore, the alignment of the two masks is critical to assure that the pattern for the conductive lines aligns with the pattern of the vias. This requires a relatively large tolerance while the via may not extend over the full width of the conductive line.
The metal that is used to construct the interconnect metal features is selected based on such performance characteristics as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing. For these reasons copper is often selected due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. Copper interconnects should therefore be encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate. A typical barrier layer is formed deposited using rf sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN. The barrier layer can also be used to improve the adhesion of the subsequent overlying tungsten layer. A barrier layer is preferably about 100 and 500 angstrom thick and more preferably about 300 angstrom thick.
Copper typically has low adhesive strength to various insulating layers and the difficulty inherent in masking and etching the blanket copper layer into intricate circuit structures. Copper is also very difficult to process using RIE technology, as a consequence of which a method that uses CMP for copper wire formation offers significant advantages. To polish a buried copper wiring formation at a high polishing rate and without damaging the surface, the copper etch rate must be raised by increasing the amount of the component that is responsible for copper etching that is contained in the polishing slurry. If the component continues to be increased, the etching will occur isotropically whereby buried copper is etched away, causing dishing in the wiring. Thus, it is difficult to form a highly reliable LSI wiring made of copper.
To further enhance the adhesion of a copper interconnect line to the surrounding layer of dielectric or insulation, a seed layer is deposited over the barrier layer. A seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using copper or a copper alloy as the source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas. The minimum thickness of a seed layer is about 50 Angstrom, this thickness is required to achieve a reliable gap fill.
FIG. 1 shows a cross section of a metal interconnect pattern created using Prior Art technology. A metal interconnect pattern 12 is formed in a surface 10, typically the surface of a layer of dielectric or insulation or the surface of a semiconductor substrate. Trenches 12, in this case a damascene or dual damascene opening, have been created in the conventional manner. A barrier layer 14 has been deposited over the sidewalls of the openings 12; a seed layer 16 of pure copper has been deposited over the barrier layer 14. A layer 18 of copper has been blanket deposited over the surface of the seed layer 16 thereby including the trenches 12 that have been created in layer 10. The excess copper is removed using CMP technology down to the level of the surface of layer 10 resulting in a network 18 of interconnect metal of copper (see FIG. 2) that is surrounded by the seed layer 16 and the barrier layer 14 inside the trenches for the interconnect lines.
Of particular concern for the formation of damascene patterns are the regions that have been highlighted as 15 in FIG. 1. The upper edge of the trench 12 is characterized by sharp angles 15 at the intersect of the sidewalls of the trenches 12 with the surface of the layer 10 in which the trenches 12 have been formed. Due to these sharp angles 15, the regions 17 in the immediate vicinity to the angles 15 that form the upper perimeter of the completed damascene interconnect lines are under considerable stress, a stress that is essentially introduced by the abrupt transition from surface area (on the surface of layer 10) to the sidewalls of the trenches 12. Any effort that results in a more gradual transition of the barrier (14), seed (16) and overlying layer of copper from the surface area of layer 10 into the trenches 12 will result in a reduction of the stress pattern in regions 17 of the created interconnect lines.
The process that is shown in FIG. 1 and 2 is applied to 0.18 um (and smaller) CMOS technology. The polishing of the copper metal lines uses, as stated, CMP technology, which results in frequent damage to the surface of the polished copper lines of damascene structures. One of the underlying reasons for this damage is poor adhesion of the deposited copper to the surface of the surrounding trench. The invention addresses this concern and provides a method that improves the copper adhesion.
U.S. Pat. No. 5,960,320 (Park), U.S. Pat. No. 5,705,430 (Avanzino et al.) and U.S. Pat. No. 5,950,102 (Lee) show the dual damascene process. However, these patents do not show the rounded trench corners.
U.S. Pat. No. 5,753,967 (Lin) shows a dual damascene Process with spacers.
U.S. Pat. No. 5,939,335 (Arndt et al.) shows a damascene process with rounded bottom trench corners. However, this reference differs from the invention.